Modern, high speed digital computers and the sophisticated software running on them require ever-increasing amounts of volatile random access memory (RAM). As bus and clock speeds increase, the electrical drive requirements for servicing a number of memory devices become much more stringent than when slower memory was in use.
The operating speed of a memory system is largely determined by the electrical interconnections between the memory controller and the memory devices, or the bus. As the data rate increases, the signal propagation times through the interconnections are no longer negligible compared to the transition time of the signals. At high bus speeds, those interconnections behave as transmission line networks. The response characteristics of such transmission line networks define the maximum usable speed of the memory bus.
In the current generation of memory packaging technology, the amount of memory physically available on a single card or module is controlled by two factors: the capacity of the memory devices (chips) themselves and the number of electrical connections that physically may be made to the module. The number of cards or modules which may be daisy chained is dependent solely upon the capacity of the line drivers or receivers. To ensure fast memory cycle times, extremely shore, fast rise pulses are used.
For example, in conventional random access memory systems, because only one bit can exist on the bus during a certain time interval, the bus speed is mainly determined by the signal setup time of the bus. As a result, the highest data rate that such bus can currently achieve in PC memory systems is 266 Mbits per second. Usually, no impedance-matching termination is required or provided in such a conventional RAM system.
To achieve even higher bus speeds and, at the same time, allow for larger memory capacities, impedance controlled types of buses must be adopted. For example, RAMBUS.RTM. technology features a memory configuration wherein memory devices are disposed (packaged) on up to three RAMBUS Inline Memory Module (RIMM) cards all interconnected on a mother board by a high speed data bus. One or more termination components are placed on the mother board at the physical end of the bus.
In operation, address/data lines leave driver circuits on the mother board and enter a first RIMM card in the memory chain. These same address/data lines must leave the RIMM via a complete, second set of connections. This routing continues through a second and third RIMM module before the driver lines reach their terminations. This memory/bus configuration allows very fast transit signals to be transmitted between a memory controller and a data storing device over relatively long buses. These buses allow multiple bits to propagate simultaneously down each line of the bus, thereby achieving access data rates of 800 Mbits per second. Even higher bus rates appear feasible in the future.
One most important feature of such buses is that the effective impedance of the signal propagation paths is well controlled, and one end of the bus is terminated to the characteristic impedance of the bus in order to maintain signal fidelity and signal integrity.
In systems adopting such buses, the amplitude of the driving signals are generally much smaller than amplitudes of conventional digital signals. This is due to the limitation on the driving strength (dv/dt) of the devices.
All of the above mentioned factors make the reliable operation of such memory buses very dependent upon controlling the impedance of the interconnections along the bus. Any impedance mismatches along the signal transmission path result in signal degradations which, in turn, may lead to errors in data transmissions. At the same time, maintenance of accurate timing among all the signal bits and clocks is also extremely critical to reliable data transmission. For this reason, minimizing signal-to-clock delay difference (data to clock skew) is another important requirement for such buses.
Prior art memory system designs generally consist of a memory controller, a clock driver and bus terminations all mounted on the mother board with up to three memory slots between the controller and the termination. The data signals must pass through every module and also through a total of six edge connectors before they reach the termination. Because of their design, current edge connectors introduce impedance mismatches and crosstalk which degrade signal quality and therefore limit the performance of the signal channels.
The inclusion of the terminations on the memory modules themselves also provides several types of performance improvement. First, because only a single set of contacts need be used (i.e., there is no need to have the bus lines exit the module), the additional contact capacity may be devoted to addressing capability for even greater amounts of memory on a single card or module. For example, current RAMBUS.RTM. technology RIMM cards support only eight or sixteen memory chips with a total capacity of no more than 256 Mbits per card. The memory modules of the present invention, however, can hold up to 32 chips per card, thereby providing a double to quadruple improvement in memory capacity. By eliminating essentially half of the required contacts, an even greater number of chips (e.g., 64 chips) may be packaged on a single card.
Total bus path length is significantly reduced because more memory may be placed on a single card physically much closer to the driver circuits than has heretofore been possible. Even more improvement is obtained because the extra passage of signals through exit contacts is eliminated. Also eliminated is that portion of the bus path between the memory modules and the external terminator resistors of the prior art.
In addition, this inventive design may reduce the design complexity and manufacturing cost of the mother board. For memory systems having one to three memory modules, using a terminated module as the last module helps to achieve maximum system performance.
The present invention also allows integration of all of the memory chips that a channel can have onto a single, terminated module, which leads to better system integrity and lower cost. The inventive, self-terminated module needs only half of the I/O connections of a conventional module of the prior art. Using a conventional prior art connector on a module, two channels of memory can be integrated onto one module, which yields increased bandwidth and double the memory capacity.
When the inventive, self-terminating memory modules are combined with innovative pin/hole interconnection technology, densities are achieved that are much higher than have been possible heretofore. This allows far more memory to be packaged on a single memory module or card. This means that more memory capacity may be deployed closer to the line drivers/receivers, thereby reducing path lengths, especially when a memory module is self terminated.
Thermal management structures may be included on the high-density, self-terminated memory modules. These structures are described in detail in copending U.S. patent application, Ser. No. 09/461,065, filed concurrently herewith.
It is, therefore, an object of the invention to provide a compact, high density memory card with up to 64 memory chips supported thereon.
It is an additional object of the invention to provide a high density memory module utilizing a novel high density connector technology.
It is another object of the invention to provide a high density memory module with bus terminations provided on the memory module itself.
It is a still further object of the invention to provide a high density memory module which can operatively reduce data path lengths, thereby helping ease driver electrical requirements in a high speed digital computer or the like.
It is another object of the invention to provide a high density memory module made from detachable sub-modules which may be temporarily connected together for testing and/or burn-in and then, optionally, attached by soldering, electrically adhering, or performing a similar process.
It is yet another object of the invention to provide a single, high-density memory module containing all of the memory capacity supported by a single bus channel or dual bus channels.